1. MAB
  2. Space Segment
  3. Spacecraft Bus Element
  4. Command & Data Handling Subsystem (C&DH)

4.4.10 - Command & Data Handling Subsystem (C&DH)

4.4.10-6 Level 2 Tasks

Tasks Applicable Mission Phases Description SFWC Artifacts References
4.4.10-6-1 Ensure reliability engineering analyses demonstrate that design life and mean mission duration requirements are satisfied Phase B | Phase C | Phase D1 | Ensure worst-case analyses, component stress levels, failure mode and effects critical analysis and reliability analyses support mission life. Ensure independent risk assessment performed of all identified single point failures. Evaluate electrical and mechanical worst case design for boxes/components. Ensure preliminary results reported at Preliminary Design Review, and updated/final results reported at Critical Design Review. NA NA Space Vehicle Systems Engineering Handbook, TOR-2006(8506)-4494; Mission Assurance Guide, TOR-2007(8546)-6018, Rev B
4.4.10-6-2 Ensure subsystem specific analyses demonstrate that design requirements are satisfied Phase B | Phase C | Phase D1 | Examine analysis results and methodologies of thermal, coupled loads, link, radiation, slosh, software throughput, etc. as applicable. NA NA Space Vehicle Systems Engineering Handbook, TOR-2006(8506)-4494; Mission Assurance Guide, TOR-2007(8546)-6018, Rev B
4.4.10-6-3 Ensure independent modeling and simulation applicable to the subsystem design are performed Phase A | Phase B | Phase C | Phase D1 | Ensure areas of design and/or operational risk in the subsystem are identified which would benefit from an independent analysis or simulations to validate contractor predictions and tradeoffs. Examples are circuit analysis, thermal, coupled loads analysis. NA NA Space Vehicle Systems Engineering Handbook, TOR-2006(8506)-4494; Mission Assurance Guide, TOR-2007(8546)-6018, Rev B
4.4.10-6-4 Ensure detailed electrical analyses are adequate and complete Phase B | Phase C | Parameters may include (depending upon circuit): worst case voltage levels, worst case timing, ensure that signals do not cross-talk or interfere with each other, stability analysis, performance analysis, etc. For PDR , ensure provision of preliminary estimates: Address items with low margin. For CDR, ensure update and show margin in all cases. (Expect combination of test data and analysis, to demonstrate end-of-life effects). Worst-case-circuit analyses should apply the extreme value analysis method, and only on approved exceptions use other methods (e.g., Monte Carlo). NA NA Space Vehicle Systems Engineering Handbook, TOR-2006(8506)-4494
4.4.10-6-5 Ensure address of all performance items having low margin using test data and analysis to demonstrate acceptability Phase B | Phase C | Critical areas may include: Processor computational throughput (including I/O), Data bus throughput, command latency, memory margin, board space, connector pins, data and/or control channels (e.g. analog samples). NA NA Space Vehicle Systems Engineering Handbook, TOR-2006(8506)-4494; SW Utilization Limits of SCP Computational Throughput capacity (TOR-2004(3000)-3172)